The fabrication of silicon based solar cells requires a number of specialized processes to occur in a specific order. Generally these processes include single crystalline silicon ingots grown in crystal growing furnaces or cast into multi-crystalline blocks in “directional solidification” furnaces. The result of these processes are long “sausage-shaped” single crystal masses called ingots, or multi-crystalline blocks, from which thin slices of silicon are cut transversely with “wire saws” to form rough solar cell wafers. These wafers, whether made up of a single crystal or multiple crystals conjoined together, are then processed to form smooth wafers in the 150 to 330 micrometer range of thickness. Because of the scarcity of suitable silicon, the current trend is towards making the wafers thinner, typically 140-180 micrometers thick.
Finished raw wafers are then processed into functioning solar cells, capable of generating electricity by the photovoltaic effect. Wafer processing starts with various cleaning and etching operations, followed by a 2-stage process called diffusion which creates a semi-conducting “p-n”, junction diode, followed by a third process in which Silver and Aluminum paste-based coatings are screen printed on the wafer front and back sides, and then fired into the p-n junction grid and back contact layer, where they act as ohmic collectors and grounds, respectively.
The diffusion process broadly comprises two stages: a first stage of applying (coating) and drying one or more types of dopant materials to the front and/or back side of the wafers, followed by a second stage of heating (firing) the coated wafers in a diffusion furnace, chamber, or heating zone, to cause diffusion of the dopant composition into the Si (or other advanced material) wafer substrate to form the p-n junction layer, or back contact layer. This invention is directed to improved diffusion furnaces and firing processes, schedules and thermal profiles. The following is a summary of the subsequent steps of processing diffusion fired wafers, which puts the invention into context.
Diffusion occurs at high temperatures in the presence of various phosphorous (P) or boron (B) sources. The P is used to produce p-type junctions on a top surface of a wafer, while B is used on the back side surface for n-type junctions. Considering P sources by way of example, the P may be provided as a sprayed liquid of dilute phosphoric acid or a vapor of phosphorous oxichloride (POCl3) created by bubbling nitrogen, N2, through liquid POCL3. After drying and firing, the P-doped Si forms the “emitter” layer of the photovoltaic cell, that is, the layer that emits electrons upon exposure to sunlight (the normal photon source). These electrons are collected by a fine web of screen printed metal contacts that are sintered into the surface of the cell by a metallization furnace, as mentioned above.
To enhance the ability to form low resistance screen-printed metal contacts to the underlying silicon p-n junction emitter layer, a selected amount of a phosphorus compound is deposited onto the front surface of the wafer. The P is driven into the wafer via a high temperature diffusion process. Current processes typically last 20-30 minutes. The extra “electrically active” P enables the low resistance contacts to be formed. However, the formation of such contacts is at the expense of a loss in cell efficiency. The cell efficiency loss arises as a result of electron-hole pairs generated at or near the surface through the absorption of higher energy but short wave length photons. These “blue light” photons quickly recombine and are lost, thereby eliminating their contribution to the power generation of the cell.
In co-diffusion, a Boron compound is applied to the back surface of the wafer and a Phosphorous compound is applied to the top surface. The wafer is heated in a single firing to simultaneously co-diffuse both the B and the P into their respective bottom and top surfaces.
After diffusion and various cleaning, laser edge ablation, and etching processes to remove unwanted semi-conductor junctions from the sides of the wafers, the wafers are coated with an anti-reflective coating, typically silicon nitride (SiN3), generally by plasma-enhanced chemical vapor deposition (PECVD). Between some of these processes, the wafers are dried in preparation for subsequent processes in low temperature drying ovens.
The SiN3 anti-reflective coating (ARC) is deposited to a thickness of approximately ¼ the wavelength of light of 0.6 microns. After ARC application, the cells exhibit a deep blue surface color (or brown color, depending on the coating material used). The ARC minimizes the reflection of incident photons having wavelengths around 0.6 microns. The ARC SiNx coating is created in the PECVD process by mixing silane, SiH4, ammonia, NH3, and pure nitrogen, N2, gases in various concentrations in a high or low frequency microwave field. The hydrogen dissociates and diffuses very rapidly into the silicon wafer. The hydrogen has a serendipitous effect of repairing bulk defects, especially in multi-crystalline material. The defects are traps where electron-hole pairs can recombine thereby reducing cell efficiency or power output.
During subsequent IR metallization firing, elevated temperatures (above 850° C.) will cause the hydrogen to diffuse back out of the wafer. Thus, short firing times are necessary to prevent this hydrogen from ‘out-gassing’ from the wafer. It is best that the hydrogen is captured and retained within the bulk material (especially in the case of multi-crystalline material).
The back surface typically is fully covered by an Aluminum-based paste, while the front or top surface is screen printed with a fine network of silver-based lines connected to larger buss conductors to “collect” the electrons generated within the depleted region of the underlying doped Si emitter or near the surface. At the same time, the highest possible open area is left uncovered for the conversion of light into electricity. After these pastes have been dried, they are “co-fired”. The back surface Aluminum paste forms alloys while the front surface paste is sintered at high speed and at high temperature in conveyor-type metallization furnaces to form smooth, low ohmic resistance conductors on the front surface of the solar cell.
The instant invention is directed to improved diffusion firing furnaces and diffusion processes. Currently available IR conveyor furnaces for such diffusion firing processes have a long heating chamber in which a plurality of IR lamps are substantially evenly spaced apart (typically 1.5″ apart) both above and below the wafer transport system (wire mesh belt or ceramic roller conveyor). The heating zone is insulated from the outside environment with various forms of insulation, compressed insulating fiber board being the most common. The infra-red (IR) lamps increase the temperature of the incoming silicon wafers to approximately 700° C. to 950° C. This temperature is held for the 30-minute duration of the diffusion process, after which the wafers are cooled and transferred to the next downstream process operation and equipment.
Currently available diffusion furnaces typically employ one of two types of wafer transport systems: 1) a plurality of static (not-longitudinally moving), solid ceramic, rotating rollers; or 2) active (longitudinally moving) wire mesh belts, to convey the wafers through the furnace firing zone. Static, ceramic rotating-roller furnaces currently are preferred in order to minimize or prevent metallic contamination of the back surface of the wafers.
A typical conventional diffusion furnace is on the order of 400″ long, having 160, 36″-wide IR lamps placed above the rollers, with from 100-160 placed below. The total mass of the conveyor rollers is on the order of 800 lbs, and is classified as a high-mass conveyor system.
In such high-mass, static, solid, rotating roller conveyor furnaces, the IR lamps take substantial time to bring the furnace chamber up to diffusion temperature in the range of 700° C. to 950° C. The theory of operation apparently is that the heated roller mass helps keep the furnace at a more even temperature throughout, as a result of the thermal reserve provided by a large, hot mass having a substantial heat capacity. Such furnace systems are touted as being able to compensate, in the short term, for failure of one or several IR lamps, if spread throughout the furnace, since the hot rollers continue to provide heat via conduction and convection. The IR lamps below the rollers maintain the rollers hot, and the contact of the wafers with the rollers help transfer heat to the wafers by thermal contact conduction. Since the rollers at the entrance and exit are not heated by the same number of lamps as those in the center of the furnace, there is a thermal profile of the conveyor, rising at the entrance and descending at the exit.
As the demand for solar cells increases, the rates of production must increase, either by process improvements or adding furnaces into service. With respect to adding furnaces, conventional furnaces have a large footprint and the diffusion process is very slow. In large part, because of the mass of ceramic in the furnace that provides thermal energy, the IR lamps are run at from about 15-20% of maximum power. Running them at greater power levels would easily raise the temperature higher than needed for diffusion, and approach failure of metallic components (e.g., in the roller drive elements secured to the ends of the rollers). Accordingly, the “soak” period to accomplish diffusion is long—on the order of 20-30 minutes. Thus, since the furnaces are large, adding furnaces requires increased capital outlay, for buildings, the furnaces themselves, and related service facilities.
Thus, the need for faster production and greater throughput, while curbing facility capital outlay, is not being met by the current state of the art solid, rotating ceramic roller conveyor furnaces. In order to compensate, furnaces have been made laterally wider, so that multiple lines of wafers can be processed in each furnace zone. This in turn requires longer, more expensive lamps which typically experience a substantially shorter mean time to failure, thus significantly increasing operating costs.
Since there are dimensional and IR lamp cost constraints, increasing lamp density in the furnace is not generally a feasible solution. Likewise, increasing the power to the lamps is not currently feasible because higher output can result in overheating of the lamp elements, as a result of the thermal mass of the furnace, principally in the high mass solid ceramic roller conveyor system. Overheating particularly affects the external quartz tubes of the lamps. Most furnaces are thermocouple controlled. Since the IR lamps are placed side by side, on the order of 1.25″ apart, each lamp heats lamps adjacent to it. When the thermocouples detect temperatures approaching the selected diffusion temperature set point in the 700-950° C. range, they automatically cut back power to the lamps by an amount that depends on the thermal mass of the transport system (rollers or metal mesh belts). This lower power density is accompanied by substantial changes in the spectral output of the IR lamp emissions (hence a lower light flux and energy output). In turn, this reduced light flux results in the need to slow down the conveyor belt speed or lengthen the furnace (while maintaining the original belt speed), thus slowing processing. Overheating of lamps, e.g., due to thermocouple delay or failure, can cause the lamps to deform, sag and eventually fail. Lamp deformation also affects uniformity of IR output delivered to the wafers.
Accordingly, there is an unmet need in the diffusion furnace and diffusion firing process art to significantly improve net effective use of firing zone(s), to provide better control and thermal profiles throughout the entire furnace, to permit improved utilization of firing energy, to improve the speed and uniformity of the diffusion process, to reduce furnace size while retaining or improving throughput, and accomplishing these goals on a reduced furnace footprint, and lower energy, operating and maintenance costs.